Integrated circuits may use phase-locked loops (“PLLs”) to generate oscillating signals, such as signals with a clock pattern (“clock signals” or “clocks”). For high-frequency analog PLLs, generating I and Q signals in output IQ dividers in such analog PLLs may be problematic due to disparate sensitivity curves of such IQ dividers.
Accordingly, it would be desirable and useful to provide an analog PLL that overcomes one or more of the limitations associated with disparate sensitivity curves of IQ dividers.